Looking for an ASIC Verification Job? Its in your best interest to brush up on your knowledge and make sure you can convey your knowledge of ASIC Verification to the best of your abilities.
One thing I often find difficult is remembering the correct terminology to use in any given situation. That is especially true when it comes to the technology world (what is Polymorphism? Do you use a Monte-Carlo Method?). When it comes to hardware verification languages (or just general software) I know what I want from a functional point of view, and I know how to code it, but when I’m asked to describe it… well sometimes it doesn’t translate directly as written in the textbooks.
So here is a refresher course aimed at refreshing your memory with the correct jargon before an interview. It will (eventually) include links to posts about Verification basics, Methodology Basics, UVM Basics and more.
Don’t just skip over parts thinking “I know that”. The whole idea is to refresh your memory. Hopefully you do know it and because you know it so well you have long since forgotten the terms that textbooks use, preferring to “just do it” (to borrow from Nike).
Before we get to the content… Have you considered looking for a contract position? There are many reasons why you might want to consider it. We have contacts to many of Silicon Valleys top companies and are approved vendors for some of the larger companies. We can promote you to many managers currently looking for staff. Please contact us via this form for more details.
- The goal of an ASIC Verification Engineer
- Verification Milestones, from start to tapeout
- A guide to writing a good verification test plan
- Some important terminology
- Testing with different levels of testbench
- System Verilog and Object Oriented Programming
- UVM
- UVM Basics
- UVM Env Reuse
- UVM Registers
- UVM Memory models
- Clock domains and Synchronizers
- Constraints
- Coverage
